Demand for high-capacity corporate backbones, for high-speed access to the global Internet, and for trunking connections for service provider internetworking has led to a growth in clear channel T3/E3 connections that has outpaced all other types and speeds of leased lines. This growth places tremendous strain on service providers and network managers to provision and manage new T3/E3 connections. The Cisco Clear Channel T3/E3 shared port adapters (SPAs) for the Cisco 7304, 7600, and 12000 Series routers offer high-density, highly manageable T3/E3 line connectivity and termination. With integrated line-interface data service units (DSUs) that allow T3/E3 lines to be directly terminated on a Cisco Systems router, the Cisco Clear Channel T3/E3 SPAs simplify T3/E3 line management, reduce provisioning costs, and make valuable rack space available. The Cisco Clear Channel T3/E3 SPA is designed to provide direct connectivity to T3/E3 lines for full-duplex communications at the T3 rate of 44.736 MHz or E3 rate of 34.368 MHz. It is available in 2- or 4-port options. The ports are configurable as either all T3 or all E3. To support the widest range of operational environments and to offer the greatest flexibility in provisioning clear channel T3/E3 connections, the Cisco Clear Channel T3/E3 SPAs take a groundbreaking step and bring together proprietary subrate and scrambling features of T3/E3 DSU vendors Quick Eagle Networks (formerly Digital Link), Larscom, ADC Kentrox, Adtran, and Verilink. Subrate support in the Cisco Clear Channel T3/E3 SPAs maximizes the application of these products in service provider environments for tiered T3 services. By simultaneously supporting interoperability with a wide range of third-party DSU vendors, the Cisco Clear Channel T3/E3 SPAs offer the flexibility to support installed equipment without committing customers to a proprietary solution. The Cisco Clear Channel T3/E3 SPA is hot-swappable and supports service-transparent online insertion and removal (OIR), allowing removal of the SPA without impacting the interface processor and other SPAs.
